In this tutorial, we implement a simple 8-bit counter that counts from 0 to 255 with an en (enable) signal and synchronous reset. Next, we write SystemVerilog code in the editor. (a) New project file seen under Project tab, (b) ModelSim Code Editor Panel A new code editor panel, as shown in Figure 4b will appear. Right click on the file then select Edit from the context menu to start editing the file. (a) Add items to the project Window, (b) Create Project File window Write Verilog Modulesīack in the main ModelSim window within the Projects tab, notice that we have a new file added to the project as shown in Figure 4a. Click OK and return to ModelSim main window. Finally, the window should look like Figure 3b. In this tutorial, I’ve chosen the name “up_counter” Then, select the type of the file to SystemVerilog. Fill in the File Name - which should reflect the function and name of the module to be created. A new Create Project File window will appear. We can either create a new file by clicking on Create New File or add existing file by clicking on Add Existing File. A new window will appear to prompt to add project files to the project as depicted in Figure 3a. Create Project WindowĬlick OK to finish creating the project.
The Create Project window should look like this in Figure 2. Default Library Name: Leave it as work.Project Location: Browse and select the working directory created in Working Directory Section.Project Name: Set project name to ELEC402_PRJ_.Enter the Project Name, Project Location, and Default Library Name: To create a new project, go to ModelSim’s menu bar and select File → New → Project… and a Create Project window will appear. In this section, we will learn how to create a new project, use ModelSim’s built in code editor, and compile Verilog files. Once you made the directory, descend into that directory: One option is to make a ModelSim_StudentNumber directory in your home directory - where StudentNumber is your UBC student number or ECE account ID. We will create a working directory where our ModelSim project files and other generated files will live. In this section, we will setup the Linux environment ready for the tools, take care of licensing issues, and start using the tools.
To run Modelsim, use the following commands: Environment Setup ModelSim is an IDE for writing, compiling, and simulating Verilog projects. In this tutorial, I will work with SystemVerilog, but I will also refer to it as Verilog for the sake of convenience. sv filetype) are hardware description landugage files we use to construct hardware and state-machines.
This document covers how to setup the Linux environment to use ModelSim, compiling and synthesizing SystemVerilog files, and configuring ModelSim to simulate a testbench.
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